1. Field of the Invention
This invention relates to a data transfer system wherein devices such as a central processing unit (CPU), a memory and input-output control devices connected to a common bus line enable data transfer with different data transfer widths and more particularly to a system wherein a plurality of direct memory access units for handling different data transfer widths are connected to the common bus line.
With an integrated data-processing system, one or more input-output controls (hereinafter referred to as IOC) are generally connected to a data bus line with a central processing unit (hereinafter referred to as CPU) which is a central element of the system.
One or more input-output devices are connected to the IOC. Some IOCs to which are connected an input-output device such as a magnetic disk capable of transferring data at high speed have the function of direct accessing to memory without commands of the CPU.
Input-output control carried out in a data-processing system is herein defined to mean control of data transfer between the CPU or main memory and input-output devices. Data transfer is controlled by two systems: one system is to effect data transfer between an input-output device and main memory by executing an input-output instruction under control by a program; and the other is to carry out direct data transfer or direct memory access (DMA) between an input-output device and main memory independently of control by a program. The former system in which a program is executed each time one word is transferred has a lower data transfer speed than the latter or DMA system. Therefore, the former system is used with a low speed input-output device, while the latter system is used with a high speed input-output device.
The DMA system has the control function in hardware needed for data transfer between the IOC and main memory independently of control by the CPU. Upon receipt of a start command from the CPU, the DMA system undertakes data transfer between the IOC chip and main memory utilizing a cycle steal. The DMA system is operated through the following fundamental sequential steps.
(I) An input-output device is selected. The start address of transfer data and a number of words being transferred are preset in a register and word counter included in a direct memory access channel (abbreviated as "DMAC").
(II) The aforesaid start address is preset in an address register of the memory.
(III) A start command is issued from the CPU.
(IV) Data continues to be transferred until a count made by a word counter is reduced to zero. During this period, the CPU remains independent of said data transfer and can be used for any other operation than data transfer.
(V) When a count made by the word counter is reduced to zero, a termination interrupt denoting the completion of data transfer is supplied to a processor, which in turn processes said interrupt, and thereafter resumes the originally continued operation.
The above-mentioned DMA system processes input and output data far more quickly than when input and output data are processed by the execution of an input-output program by the CPU. Further advantage of the DMA system is that while data is transferred between an external device and main memory, the CPU remains idle and can take part in any other work.
In recent years, the DMA system is being required to operate at a much higher speed. One of the effective steps of ensuring the high speed data transfer by the DMA system is to increase the data width (a total bit number of data conducted through a common bus line each time).
An IOC with an expanded data transfer width can be connected to an improved data processing system of which the data transfer width is expanded, but an IOC with a narrower data transfer width cannot be connected.
In the prior art, therefore, IOCs had to be changed in design so as to be connectable to the DMA bus which is connected to the improved data transfer system, so that the IOCs can effect data transfer with an expanded data transfer width.